1. Field of the Invention
This invention relates to a semiconductor device, specifically to a layout of a semiconductor device provided with a memory cell that includes CMOS inverters.
2. Description of the Related Art
In recent years, many computer systems are incorporated in home appliances and machines, which increasingly require electronic control. A memory-embedded semiconductor device in which a memory such as a flash memory, SRAM (Static Random Access Memory) or the like is formed on a single semiconductor substrate (that is, a semiconductor die) together with a microcomputer is known as an example of such a computer system.
In order to reduce a size of the memory-embedded semiconductor device, it is required that an area of the die occupied by the SRAM which is often primarily used as a buffer memory is decreased as much as possible while an area of the die occupied by the flash memory which is required to have a large storage capacity is increased as much as possible.
For example, a memory cell shown in FIG. 1 of Japanese Patent No. 4190242 discloses a layout to minimize an area of an SRAM memory cell that includes two CMOS inverters. In the memory cell, gate wirings of the two CMOS inverters are placed close to each other and a connection between drains of transistors in each of the two inverters and a loop connection between the drains and gates of the two inverters are made using two metal layers that are upper layers of the gate wirings. The area of the memory cell can be minimized with the layout.
In some cases, however, restrictions to be explained below are imposed in forming the SRAM described above, depending on process technologies and design rules adopted. The restrictions would increase the area of the memory cell and increase the size of the memory-embedded semiconductor device in which the SRAM is formed.
For example, in order to optimize manufacturing of the flash memory that occupies a large area, process technologies (process technologies for the flash memory, for example) that are not best suitable for manufacturing the SRAM are adopted in some cases. Since the design rules are restricted due to conditions of the process technologies and a leakage current is apt to be caused between a source and a drain depending on a width of the gate wiring that constitutes the CMOS inverter in the SRAM, using a layout that requires increased width of the gate wiring (that is, gate length) is necessary to suppress the leakage current.
Also, there are cases in which flexibility in designing a wiring pattern in an uppermost metal layer is severely restricted, depending on design rules applied to metal layers used in multi-layer wirings. For example, when the design rules impose a restriction that a thick external connection electrode such as a bonding pad is to be formed of the uppermost metal layer, fine wiring pattern is not available with the uppermost metal layer.
To explain the restrictions in the design rules in the case where they are applied to the memory cell of the SRAM shown in FIG. 1 of Japanese Patent No. 4190242, a bit line has to be laid out in a second metal layer that allows fine wiring pattern although it should be otherwise laid out in the uppermost metal layer that is a third metal layer. The wiring connecting between the drains of transistors in each of the two CMOS inverters is also laid out in the second metal layer, and has to be laid out largely detoured to avoid the bit line in the same metal layer. Therefore, the layout of the second metal layer is largely expanded to increase the area of the memory cell.
This invention is directed to offer a semiconductor device that can suppress the increase in the area of the memory cell even though there are restrictions on the gate wiring due to the leakage current between the source and the drain of the transistor in the CMOS inverter constituting the SRAM or the restrictions in the design rules imposed on the metal layers used in the multi-layer wiring.